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2009 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-5611/6 ? february 2009 cmos triple bus syncfifo tm with bus-matching 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2 IDT723656 idt723666 idt723676 1 commercial temperature range idt and the idt logo are registered trademark of integrated device technology, inc. syncfifo is a trademark of integrated devi ce technology, inc. functional block diagram features ? ? ? ? ? memory storage capacity: IDT723656 ? 2,048 x 36 x 2 idt723666 ? 4,096 x 36 x 2 idt723676 ? 8,192 x 36 x 2 ? ? ? ? ? clock frequencies up to 83 mhz (8ns access time) ? ? ? ? ? two independent fifos buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports (port c receives and port b transmits) ? ? ? ? ? 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on ports b and c ? ? ? ? ? select idt standard timing (using efa , efb , ffa , and ffc flag functions) or first word fall through timing (using ora, orb, ira, and irc flag functions) ? ? ? ? ? programmable almost-empty and almost-full flags; each has five default offsets (8, 16, 64, 256 and 1024) ? ? ? ? ? serial or parallel programming of partial flags ? ? ? ? ? big- or little-endian format for word and byte bus sizes ? ? ? ? ? loopback mode on port a ? ? ? ? ? retransmit capability ? ? ? ? ? master reset clears data and configures fifo, partial reset clears data but retains configuration settings ? ? ? ? ? mailbox bypass registers for each fifo ? ? ? ? ? free-running clka, clkb and clkc may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) ? ? ? ? ? auto power down minimizes power dissipation ? ? ? ? ? available in a space-saving 128-pin thin quad flatpack (tqfp) ? ? ? ? ? pin compatible to the lower density parts, idt723626/3636/3646 ? ? ? ? ? industrial temperature range (?40 c to +85 c) is available ? ? ? ? ? green parts available, see ordering information mail 1 register programmable flag offset registers input register ram array 2,048 x 36 4,096 x 36 8,192 x 36 write pointer read pointer status flag logic input register output register ram array 2,048 x 36 4,096 x 36 8,192 x 36 write pointer read pointer status flag logic clka csa w/ r a ena mba loop port-a control logic fifo1, mail1 reset logic mrs1 mail 2 register mbf2 wenc port-c control logic fifo2, mail2 reset logic mrs2 mbf1 fifo1 fifo2 13 efb /orb aeb 18 18 ffc /irc afc b 0 -b 17 ffa /ira afa fs2 fs0/sd fs1/ sen a 0 -a 35 efa /ora aea 5611 drw01 36 36 output bus- matching output register prs2 prs1 timing mode fwft c 0 -c 17 clkb renb csb mbb port-b control logic common port control logic (b and c) be sizeb sizec clkc mbc 36 36 36 36 input bus- matching fifo1 and fifo2 retransmit logic rt1 rt2 rtm
2 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range 18-bit buses (port b transmits data, port c receives data.) fifo data can be read out of port b and written into port c using either 18-bit or 9-bit formats with a choice of big- or little-endian configurations. these devices are a synchronous (clocked) fifo, meaning each port employs a synchronous interface. all data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. the clocks for description the IDT723656/723666/723676 is a monolithic, high-speed, low-power, cmos triple bus synchronous (clocked) fifo memory which supports clock frequencies up to 83 mhz and has read access times as fast as 8ns. two independent 2,048/4,096/8,192 x 36 dual-port sram fifos on board each chip buffer data between a bidirectional 36-bit bus (port a) and two unidirectional pin configuration tqfp (pk128-1, order code: pf) top view w/ r a clkb 5611 drw02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ena clka gnd a35 a34 a33 a32 vcc a31 a30 gnd a29 a28 a27 a26 a25 a24 a23 be/ fwft gnd a22 vcc a21 a20 a19 a18 gnd a17 a16 a15 a14 a13 vcc a12 gnd a11 a10 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 102 101 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 prs2 / rt2 c17 c16 c15 c14 mbc rtm c13 c12 c11 c10 c9 c8 c7 c6 sizeb gnd c5 c4 c3 c2 c1 c0 gnd b17 b16 b15 b14 b13 b12 gnd b11 b10 csa ffa /ira efa /ora prs1 / rt1 afa aea mbf2 mba mrs1 fs0/sd clkc gnd fs1/ sen mrs2 mbb mbf1 aeb afc efb /orb ffc /irc gnd csb wenc renb a9 a8 a7 a6 gnd a5 a4 a3 a2 a1 a0 gnd b0 b1 b2 b3 b4 b5 gnd b6 b7 b9 104 103 index sizec b8 v cc v cc v cc v cc v cc v cc loop fs2
3 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 each port are independent of one another and can be asynchronous or coincident. the enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchro- nous control. communication between each port may bypass the fifos via two mailbox registers. the mailbox registers' width matches the selected bus width of ports b and c. each mailbox register has a flag ( mbf1 and mbf2 ) to signal when new mail has been stored. two kinds of reset are available on these fifos: master reset and partial reset. master reset initializes the read and write pointers to the first location of the memory array and selects serial flag programming, parallel flag program- ming, or one of five possible default flag offset settings, 8, 16, 64, 256 or 1,024. each fifo has its own, independent master reset pin, mrs1 and mrs2 . partial reset also sets the read and write pointers to the first location of the memory. unlike master reset, any settings existing prior to partial reset (i.e., programming method and partial flag default offsets) are retained. partial reset is useful since it permits flushing of the fifo memory without changing any configuration settings. each fifo has its own, independent partial reset pin, prs1 and prs2 . note that the retransmit mode, rtm pin must be low at the point a partial reset is performed. both fifo's have retransmit capability, when a retransmit is performed on a respective fifo only the read pointer is reset to the first memory location. a retransmit is performed by using the retransmit mode, rtm pin in conjunction with the retransmit pins rt1 or rt2, for each respective fifo. note that the two retransmit pins rt1 and rt2 are muxed with the partial reset pins. these devices have two modes of operation: in the idt standard mode , the first word written to an empty fifo is deposited into the memory array. a read operation is required to access that word (along with all other words residing in memory). in the first word fall through mode (fwft), the first word written to an empty fifo appears automatically on the outputs, no read operation required (nevertheless, accessing subsequent words does necessitate a formal read request). the state of the be/ fwft pin during master reset determines the mode in use. each fifo has a combined empty/output ready flag ( efa /ora and efb / orb) and a combined full/input ready flag ( ffa /ira and ffc /irc). the ef and ff functions are selected in the idt standard mode. ef indicates whether or not the fifo memory is empty. ff shows whether the memory is full or not. the ir and or functions are selected in the first word fall through mode. ir indicates whether or not the fifo has available memory locations. or shows whether the fifo has data available for reading or not. it marks the presence of valid data on the outputs. each fifo has a programmable almost-empty flag ( aea and aeb ) and a programmable almost-full flag ( afa and afc ). aea and aeb indicate when a selected number of words remain in the fifo memory. afa and afc indicate when the fifo contains more than a selected number of words. ffa /ira, ffc /irc, afa and afc are two-stage synchronized to the port clock that writes data into its array. efa /ora, efb /orb, aea , and aeb are two-stage synchronized to the port clock that reads data from its array. programmable offsets for aea , aeb , afa , afc are loaded in parallel using port a or in serial via the sd input. five default offset settings are also provided. the aea and aeb threshold can be set at 8, 16, 64, 256, and 1,024 locations from the empty boundary and the afa and afc threshold can be set at 8, 16, 64, 256 or 1,024 locations from the full boundary. all these choices are made using the fs0, fs1 and fs2 inputs during master reset. interspersed parity can also be selected during a master reset of the fifo. if interspersed parity is selected then during parallel programming of the flag offset values, the device will ignore data line a8. if non-interspersed parity is selected then data line a8 will become a valid bit. a loopback function is provided on port a. when the loop feature is selected via the loop pin, the data output from fifo2 will be directed to the data input of fifo1. if loop is selected and port a is set-up for write operation via w/ r a pin, then data output from fifo2 will be written to fifo1, but will not be placed on the output port a (a0-a35). if port a is set-up for read operation via w/ r a then data output from fifo2 will be written into fifo1 and placed onto port a (a0-a35). the loop will continue to happen provided that fifo1 is not full and fifo2 is not empty. if during a loop sequence fifo1 becomes full then any data that continues to be read out from fifo2 will only be placed on the port a (a0-a35) lines, provided that port a is set-up for read operation. if during a loop sequence the fifo2 becomes empty, then the last word from fifo2 will continue to be clocked into fifo1 until fifo1 becomes full or until the loop function is stopped. the loop feature can be useful when performing system debugging and remote loopbacks. two or more fifos may be used in parallel to create wider data paths. such a width expansion requires no additional, external components. furthermore, two IDT723656/723666/723676 fifos can be combined with unidirectional fifos capable of first word fall through timing (i.e. the supersync fifo family) to form a depth expansion. if, at any time, the fifo is not actively performing a function, the chip will automatically power down. during the power down state, supply current consumption (i cc ) is at a minimum. initiating any operation (by activating control inputs) will immediately take the device out of the power down state. the IDT723656/723666/723676 are characterized for operation from 0 c to 70 c. industrial temperature range (-40 c to +85 c) is available by special order. they are fabricated using idt?s high speed, submicron cmos technology.
4 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range pin descriptions symbol name i/o description a0-a35 port a data i/o 36-bit bidirectional data port for side a. aea port a almost- o programmable almost-empty flag synchronized to clka. it is low when the number of words in fifo2 empty flag is less than or equal to the value in the almost-empty a offset register, x2. aeb port b almost- o programmable almost-empty flag synchronized to clkb. it is low when the number of words in fifo1 empty flag is less than or equal to the value in the almost-empty b offset register, x1. afa port a almost- o programmable almost-full flag synchronized to clka. it is low when the number of empty locations full flag in fifo1 is less than or equal to the value in the almost-full a offset register, y1. afc port c almost- o programmable almost-full flag synchronized to clkc. it is low when the number of empty locations full flag in fifo2 is less than or equal to the value in the almost-full c offset register, y2. b0-b17 port b data o 18-bit output data port for side b. be/ fwft big-endian/ i this is a dual purpose pin. during master reset, a high on be will select big-endian operation. first word fall in this case, depending on the bus size, the most significant byte or word on port a is read from through select port b first (a-to-b data flow) or is written to port c first (c-to-a data flow). a low on be will select little-endian operation. in this case, the least significant byte or word on port a is read from port b first (a-to-b data flow) or is written to port c first (c-to-a data flow). after master reset, this pin selects the timing mode. a high on fwft selects idt standard mode, a low selects first word fall through mode. once the timing mode has been selected, the level on fwft must be static throughout device operation. c0-c17 port c data i 18-bit input data port for side c. clka port a clock i clka is a continuous clock that synchronizes all data transfers through port a and can be asynchronous or coincident to clkb. ffa /ira, efa /ora, afa , and aea are all synchronized to the low-to-high transition of clka. clkb port b clock i clkb is a continuous clock that synchronizes all data transfers through port b and can be asynchronous or coincident to clka. efb /orb and aeb are synchronized to the low-to-high transition of clkb. clkc port c clock i clkc is a continuous clock that synchronizes all data transfers through port c and can be asynchronous or coincident to clka. ffc /irc and afc are synchronized to the low-to-high transition of clkc. csa port a chip i csa must be low to enable to low-to-high transition of clka to read or write on port a. the a0-a35 select outputs are in the high-impedance state when csa is high. csb port b chip i csb must be low to enable a low-to-high transition of clkb to read data on port b. the b0-b17 select outputs are in the high-impedance state when csb is high. efa /ora port a empty/ o this is a dual function pin. in the idt standard mode, the efa function is selected. efa indicates output ready whether or not the fifo2 memory is empty. in the fwft mode, the ora function is selected. ora flag indicates the presence of valid data on the a0-a35 outputs, available for reading. efa /ora is synchronized to the low-to-high transition of clka. efb /orb port b empty/ o this is a dual function pin. in the idt standard mode, the efb function is selected. efb indicates output ready flag whether or not the fifo1 memory is empty. in the fwft mode, the orb function is selected. orb indicates the presence of valid data on the b0-b17 outputs, available for reading. efb /orb is synchronized to the low-to-high transition of clkb. ena port a enable i ena must be high to enable a low-to-high transition of clka to read or write data on port a. ffa /ira port a full/ o this is a dual function pin. in the idt standard mode, the ffa function is selected. ffa indicates input ready flag whether or not the fifo1 memory is full. in the fwft mode, the ira function is selected. ira indicates whether or not there is space available for writing to the fifo1 memory. ffa /ira is synchronized to the low-to-high transition of clka. ffc /irc port c full/ o this is a dual function pin. in the idt standard mode, the ffc function is selected. ffc indicates input ready flag whether or not the fifo2 memory is full. in the fwft mode, the irc function is selected. irc indicates whether or not there is space available for writing to the fifo2 memory. ffc /irc is synchronized to the low-to-high transition of clkc.
5 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 pin descriptions (continued) symbol name i/o description fs0/sd flag offset select 0/ i fs1/ sen and fs0/sd are dual-purpose inputs used for flag offset register programming. during master reset, serial data fs1/ sen and fs0/sd, together with fs2, select the flag offset programming method. three offset register programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or 1,024), fs1/ sen flag offset select 1/ i parallel load from port a, and serial load. serial enable when serial load is selected for flag offset register programming, fs1/ sen is used as an enable synchronous to fs2 (1) flag offset select 2 i the low-to-high transition of clka. when fs1/ sen is low, a rising edge on clka load the bit present on fs0/sd into the x and y registers. the number of bit writes required to program the offset registers is 44 for the IDT723656, 48 for the idt723666, and 52 for the idt723676. the first bit write stores the y-register (y1) msb and the last bit write stores the x-register (x2) lsb. loop loopback select i this pin selects the loopback feature for port a. during loopback data from fifo2 will be directed to the input of fifo1. to initiate a loop the loop pin must be held low and the ena pin must be high. mba port a mailbox i a high level on mba chooses a mailbox register for a port a read or write operation. when the a0-a35 select outputs are active, a high level on mba selects data from the mail2 register for output and a low level selects fifo2 output-register data for output. mbb port b mailbox i a high level on mbb chooses a mailbox register for a port b read operation. when the b0-b17 outputs are select active, a high level on mbb selects data from the mail1 register for output and a low level selects fifo1 output register data for output. mbc port c mailbox i a high level on mbc chooses the mail2 register for a port c write operation. this pin must be high during select ma ster reset. mbf1 mail1 register o mbf1 is set low by a low-to-high transition of clka that writes data to the mail1 register. writes to the mail1 flag register are inhibited while mbf1 is low. mbf1 is set high by a low-to-high transition of clkb when a port b read is selected and mbb is high. mbf1 is set high following either a master or partial reset of fifo1. mbf2 mail2 register o mbf2 is set low by a low-to-high transition of clkc that writes data to the mail2 register. writes to the mail2 flag regi ster are inhibited while mbf2 is low. mbf2 is set high by a low-to-high transition of clka when a port a read is selected and mba is high. mbf2 is set high following either a master or partial reset of fifo2. mrs1 master reset i a low on this pin initializes the fifo1 read and write pointers to the first location of memory and sets the port b output register to all zeroes. a low-to-high transition on mrs1 selects the programming method (serial or parallel) and one of five programmable flag default offsets for fifo1 and fifo2. it also configures ports b and c for bus size and endian arrangement. four low-to-high transitions of clka and four low-to-high transitions of clkb must occur while mrs1 is low. mrs2 master reset i a low on this pin initializes the fifo2 read and write pointers to the first location of memory and sets the port a output register to all zeroes. a low-to-high transition on mrs2 , toggled simultaneously with mrs1 , selects the programming method (serial or parallel) and one of the five flag default offsets for fifo2. four low-to-high transitions of clka and four low-to-high transitions of clkc must occur while mrs2 is low. prs1 / partial reset/ i this pin is muxed for both partial reset and retransmit operations, it is used in conjunction with the rtm pin . if rtm rt1 retransmit fifo1 is in a low condition, a low on this pin performs a partial reset on fifo1 and initializes the fifo1 read and write pointers to the first location of memory and sets the port b output register to all zeroes. during partial reset, the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. if rtm is high, a low on this pin performs a retransmit and initializes the fifo1 read pointer only to the first memory location. prs2 / partial reset/ i this pin is muxed for both partial reset and retransmit operations, it is used in conjunction with the rtm pi n. if rtm rt2 retransmit fifo2 is in a low condition, a low on this pin performs a partial reset on fifo2 and initializes the fifo2 read and write selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. if rtm is high, a low on this pin performs a retransmit and initializes the fifo2 read pointer only to the first memory location. renb port b read enable i renb must be high to enable a low-to-high transition of clkb to read data on port b. rtm retransmit mode i this pin is used in conjunction with the rt1 and rt2 pins. when rtm is high a retransmit is performed on fifo1 or fifo2 respectively.
6 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range sizeb (1) port b i sizeb determines the bus width of port b. a high on this pin selects byte (9-bit) bus size. a low on this pin bus size select selects word (18-bit) bus size. sizeb works with sizec and be to select the bus size and endian arrangement for ports b and c. the level of sizeb must be static throughout device operation. sizec (1) port c i sizec determines the bus width of port c. a high on this pin selects byte (9-bit) bus size. a low on this pin bus size select selects word (18-bit) bus size. sizec works with sizeb and be to select the bus size and endian arrangement for ports b and c. the level of sizec must be static throughout device operation. wenc port c write enable i wenc must be high to enable a low-to-high transition of clkc to write data on port c. w/ r a port a write/ i a high selects a write operation and a low selects a read operation on port a for a low-to-high transition of read select clka. the a0-a35 outputs are in the high impedance state when w/ r a is high. pin descriptions (continued) symbol name i/o description note: 1. fs2, sizeb and sizec inputs are not ttl compatible. these inputs should be tied to gnd or v cc .
7 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 symbol rating commercial unit v cc supply voltage range ?0.5 to +7.0 v v i (2) input voltage range ?0.5 to v cc +0.5 v v o (2) output voltage range ?0.5 to v cc +0.5 v i ik input clamp current (v i < 0 or v i > v cc ) 20 ma i ok output clamp current (v o = < 0 or v o > v cc ) 50 ma i out continuous output current (v o = 0 to v cc ) 50 ma i cc continuous current through v cc or gnd 400 ma t stg storage temperature range ?65 to 150 c notes: 1. stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress rat ings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-m aximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded provided the input and output current ratings are observed. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v v ih high level input voltage 2 ? v v il low-level input voltage ? 0.8 v i oh high-level output current ??4ma i ol low-level output current ?8ma t a operating free-air temperature 0 70 c recommended operating conditions notes: 1. all typical values are at v cc = 5v, t a = 25 c. 2. for additional i cc information, see figure 1, typical characteristics: supply current (i cc ) vs. clock frequency (f s ). 3. characterized values, not currently tested. 4. industrial temperature range is available by special order. electrical characteristics over recommended operating free- air temperature range (unless otherwise noted) IDT723656 idt723666 idt723676 commercial t clk = 12, 15ns symbol parameter test conditions min. typ. (1) max. unit v oh output logic "1" voltage v cc = 4.5v, i oh = ?4 ma 2.4 ? ? v v ol output logic "0" voltage v cc = 4.5v, i ol = 8 ma ? ? 0.5 v i li input leakage current (any input) v cc = 5.5v, v i = v cc or 0 ? ? 10 a i lo output leakage current v cc = 5.5v, v o = v cc or 0 ? ? 10 a i cc2 (2) standby current (with clka, clkb and clkc running) v cc = 5.5v, v i = v cc ?0.2v or 0v ? ? 8 ma i cc3 (2) standby current (no clocks running) v cc = 5.5v, v i = v cc ?0.2v or 0v ? ? 1 ma c in (3) input capacitance v i = 0, f = 1 mhz ? 4 ? pf c out (3) output capacitance v o = 0, f = 1 mhz ? 8 ? pf
8 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range figure 1. typical characteristics: supply current (i cc ) vs. clock frequency (f s ) 010 203040506070 0 50 100 150 200 250 300 v cc = 5.0v f s ? clock frequency ? mhz i cc(f) supply current ma f data = 1/2 f s t a = 25 o c c l = 0 pf v cc = 4.5v v cc = 5.5v 5611 drw02a 80 90 determining active current consumption and power dissipation the i cc(f) current for the graph in figure 1 was taken while simultaneously reading and writing a fifo on the IDT723656/723666/723676 wit h clka, clkb and clkc set to f s . all data inputs and data outputs change state during each clock cycle to consume the highest supply current. data outputs w ere disconnected to normalize the graph to a zero capacitance load. once the capacitance load per data-output channel and the numb er of these device's inputs driven by ttl high levels are known, the power dissipation can be calculated with the equation below. calculating power dissipation with i cc(f) taken from figure 1, the maximum power dissipation (p t ) of these fifos may be calculated by: p t = v cc x [i cc (f) + (n x ? i cc x dc)] + (c l x v cc 2 x f o ) n where: n = number of inputs driven by ttl levels ? i cc = increase in power supply current for each input at a ttl high level dc = duty cycle of inputs at a ttl high level of 3.4v c l = output capacitance load f o = switching frequency of an output
9 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 timing requirements over recommended ranges of supply voltage and operating free-air temperature commercial IDT723656l12 IDT723656l15 idt723666l12 idt723666l15 idt723676l12 idt723676l15 symbol parameter min. max. min. max. unit f s clock frequency, clka, clkb, or clkc ? 83 ? 66.7 mhz t clk clock cycle time, clka, clkb, or clkc 12 ? 15 ? ns t clkh pulse duration, clka, clkb, or clkc high 5 ? 6 ? ns t clkl pulse duration, clka, clkb, or clkc low 5 ? 6 ? ns t ds setup time, a0-a35 before clka and c0-c17 before clkc 3?4? ns t ens1 setup time, csa and w/ r a before clka ; csb before clkb 4 ? 4.5 ? ns t ens2 setup time, ena, and mba before clka ; renb and mbb before clkb ; 3 ? 4.5 ? ns wenc and mbc before clkc t rsts setup time, mrs1 , mrs2 , prs1 , prs2, rt1 or rt2 low before clka or clkb (1) 5?5? ns t fss setup time, fs0, fs1, fs2 before mrs1 and mrs2 high 7.5 ? 7.5 ? ns t bes setup time, be/ fwft before mrs1 and mrs2 high 7.5 ? 7.5 ? ns t sds setup time, fs0/sd before clka 3?4? ns t sens setup time, fs1/ sen before clka 3?4? ns t fws setup time, be/ fwft before clka 0?0? ns t rtms setup time, rtm before rt1 ; rtm before rt2 5?5? ns t dh hold time, a0-a35 after clka and c0-c17 after clkc 0.5 ? 1 ? ns t enh hold time, csa , w/ r a, ena, and mba after clka ; csb , renb, and mbb after 0.5 ? 1 ? ns clkb ; wenc and mbc after clkc t rsth hold time, mrs1 , mrs2 , prs1, prs2 , rt1 or rt2 low after clka or clkb (1) 4?4? ns t fsh hold time, fs0, fs1, fs2 after mrs1 and mrs2 high 2 ? 2 ? ns t beh hold time, be/ fwft after mrs1 and mrs2 high 2 ? 2 ? ns t sdh hold time, fs0/sd after clka 0.5 ? 1 ? ns t senh hold time, fs1/ sen high after clka 0.5 ? 1 ? ns t sph hold time, fs1/ sen high after mrs1 and mrs2 high 2 ? 2 ? ns t rtmh hold time, rtm after rt1 ; rtm after rt2 5?5? ns t skew1 (2) skew time, between clka and clkb for efb /orb and ffa /ira; between clka 5 ? 7.5 ? ns and clkc for efa /ora and ffc /irc t skew2 (2,3) skew time, between clka and clkb for aeb and afa ; between clka and 12 ? 12 ? ns clkc for aea and afc notes: 1. requirement to count the clock edge as one of at least four needed to reset a fifo. 2. skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship a mong clka cycle, clkb cycle, and clkc cycle. 3. design simulated, not tested. 4. industrial temperature range is available by special order. (commercial: v cc = 5v 10%, t a = 0 c to +70 c)
10 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range switching characteristics over recommended ranges of supply voltage and operating free-air temperature, cl = 30pf commercial IDT723656l12 IDT723656l15 idt723666l12 idt723666l15 idt723676l12 idt723676l15 symbol parameter min. max. min. max. unit t a access time, clka to a0-a35 and clkb to b0-b17 2 8 2 10 ns t wff propagation delay time, clka to ffa /ira and clkc to ffc /irc 2 8 2 8 ns t ref propagation delay time, clka to efa /ora and clkb to efb /orb 1 8 1 8 ns t pae propagation delay time, clka to aea and clkb to aeb 1818ns t paf propagation delay time, clka to afa and clkc to afc 1818ns t pmf propagation delay time, clka to mbf1 low or mbf2 high, clkb to mbf1 0808ns high, and clkc to mbf2 low t pmr propagation delay time, clka to b0-b17 (1) and clkc to a0-a35 (2) 28 210ns t mdv propagation delay time, mba to a0-a35 valid and mbb to b0-b17 valid 2 8 2 10 ns t rsf propagation delay time, mrs1 or prs1 low to aeb low, afa high, and mbf1 110115ns high and mrs2 or prs2 low to aea low, afc high, and mbf2 high t en enable time, csa or w/ r a low to a0-a35 active and csb low to b0-b17 active 2 6 2 10 ns t dis disable time, csa or w/ r a high to a0-a35 at high impedance and csb high 1 6 1 8 ns to b0-b17 at high impedance notes: 1. writing data to the mail1 register when the b0-b17 outputs are active and mbb is high. 2. writing data to the mail2 register when the a0-a35 outputs are active and mba is high. 3. industrial temperature range is available by special order. (commercial: v cc = 5v 10%, t a = 0 c to +70 c)
11 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 signal description master reset ( mrs1 , mrs2 ) after power up, a master reset operation must be performed by providing a low pulse to mrs1 and mrs2 simultaneously. afterwards, the fifo1 memory of the IDT723656/723666/723676 undergoes a complete reset by taking its associated master reset ( mrs1 ) input low for at least four port a clock (clka) and four port b clock (clkb) low-to-high transitions. the fifo2 memory undergoes a complete reset by taking its associated master reset ( mrs2 ) input low for at least four port a clock (clka) and four port c clock (clkc) low-to-high transitions. the master reset inputs can switch asynchronously to the clocks. a master reset initializes the associated read and write pointers to the first location of the memory and forces the full/input ready flag ( ffa /ira, ffc /irc) low, the empty/output ready flag ( efa /ora, efb / orb) low, the almost-empty flag ( aea , aeb ) low and the almost-full flag ( afa , afc ) high. a master reset also forces the associated mailbox flag ( mbf1 , mbf2 ) of the parallel mailbox register high. after a master reset, the fifo's full/input ready flag is set high after two write clock cycles. then the fifo is ready to be written to. a low-to-high transition on the fifo1 master reset ( mrs1 ) input latches the value of the big-endian (be) input for determining the order by which bytes are transferred through ports b and c. it also latches the values of the flag select (fs0, fs1 and fs2) inputs for choosing the almost-full and almost-empty offsets and programming method. a low-to-high transition on the fifo2 master reset ( mrs2 ) clears the flag offset registers of fifo2 (x2, y2). a low-to-high transition on the fifo2 master reset ( mrs2 ) together with the fifo1 master reset input ( mrs1 ) latches the value of the big-endian (be) input for ports b and c and also latches the values of the flag select (fs0, fs1 and fs2) inputs for choosing the almost- full and almost-empty offsets and programming method (for details see table 1, flag programming, and almost-empty and almost-full flag offset program- ming section). the relevant master reset timing diagrams can be found in figure 4 and 5. note that mbc must be high during master reset (until ffa /ira and ffc /irc go high). mba and mbb are "don't care" inputs 1 during master reset. partial reset ( prs1 , prs2 ) the fifo1 memory of these devices undergoes a limited reset by taking its associated partial reset ( prs1 ) input low for at least four port a clock (clka) and four port b clock (clkb) low-to-high transitions. the fifo2 memory undergoes a limited reset by taking its associated partial reset ( prs2 ) input low for at least four port a clock (clka) and four port c clock (clkc) low- to-high transitions. the rtm pin must be low during the time of partial reset. the partial reset inputs can switch asynchronously to the clocks. a partial reset initializes the internal read and write pointers and forces the full/input ready flag ( ffa /ira, ffc /irc) low, the empty/output ready flag ( efa /ora, efb / orb) low, the almost-empty flag ( aea , aeb ) low, and the almost-full flag ( afa , afc ) high. a partial reset also forces the mailbox flag ( mbf1 , mbf2 ) of the parallel mailbox register high. after a partial reset, the fifo?s full/input ready flag is set high after two write clock cycles. whatever flag offsets, programming method (parallel or serial), and timing mode (fwft or idt standard mode) are currently selected at the time a partial reset is initiated, those settings will remain unchanged upon completion of the reset operation. a partial reset may be useful in the case where reprogramming a fifo following a master reset would be inconvenient. see figure 6 and 7 for partial reset timing diagrams. retransmit ( rt1 , rt2 ) the fifo1 memory of these devices undergoes a retransmit by taking its associated retransmit ( rt1 ) input low for at least four port a clock (clka) and four port b clock (clkb) low-to-high transitions. the retransmit initializes the read pointer of fifo1 to the first memory location. the fifo2 memory undergoes a retransmit by taking its associated retransmit ( rt2 ) input low for at least four port a clock (clka) and four port c clock (clkc) low-to-high transitions. the retransmit initializes the read pointer of fifo1 to the first memory location. the rtm pin must be high during the time of retransmit. note that the rt1 input is muxed with the prs1 input, the state of the rtm pin determining whether this pin performs a retransmit or partial reset. also, the rt2 input is muxed with the prs2 input, the state of the rtm pin determining whether this pin performs a retransmit or partial reset. see figures 30, 31, 32 and 33 for retransmit timing diagrams. big-endian/first word fall through ( be/ fwft ) ? endian selection this is a dual purpose pin. at the time of master reset, the be select function is active, permitting a choice of big- or little-endian byte arrangement for data written to port c or read from port b. this selection determines the order by which bytes (or words) of data are transferred through those ports. for the following illustrations, note that both ports b and c are configured to have a byte (or a word) bus size. a high on the be/ fwft input when the master reset ( mrs1 , mrs2 ) inputs go from low to high will select a big-endian arrangement. when data is moving in the direction from port a to port b, the most significant byte (word) of the long word written to port a will be read from port b first; the least significant byte (word) of the long word written to port a will be read from port b last. when data is moving in the direction from port c to port a, the byte (word) written to port c first will be read from port a as the most significant byte (word) of the long word; the byte (word) written to port c last will be read from port a as the least significant byte (word) of the long word. a low on the be/ fwft input when the master reset ( mrs1 , mrs2 ) inputs go from low to high will select a little-endian arrangement. when data is moving in the direction from port a to port b, the least significant byte (word) of the long word written to port a will be read from port b first; the most significant byte (word) of the long word written to port a will be read from port b last. when data is moving in the direction from port c to port a, the byte (word) written to port c first will be read from port a as the least significant byte (word) of the long word; the byte (word) written to port c last will be read from port a as the most significant byte (word) of the long word. refer to figure 2 and 3 for illustrations of the be function. see figure 4 (fifo1 master reset) and 5 (fifo2 master reset) for endian select timing diagrams. ? timing mode selection after master reset, the fwft select function is available, permitting a choice between two possible timing modes: idt standard mode or first word fall through (fwft) mode. once the master reset ( mrs1 , mrs2 ) input is high, a high on the be/ fwft input during the next low-to-high transition of clka (for fifo1) and clkc (for fifo2) will select idt standard mode. this mode uses the empty flag function ( efa , efb ) to indicate whether or not there are any words present in the fifo memory. it uses the full flag function ( ffa , ffc ) to indicate whether or not the fifo memory has any free space for writing. in idt standard mode, every word read from the fifo, including the first, must be requested using a formal read operation. note: 1. either a high or low can be applied to a "don't care" input with no change to the logical operation of the fifo. nevertheles s, inputs that are temporarily "don't care" (along with unused inputs) must not be left open, rather they must be either high or low.
12 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range fs2 fs1/ sen fs0/sd mrs1 mrs2 x1 and y1 reglsters (1) x2 and y2 reglsters (2) hh h x64 x hh hx x64 hh l x16 x hh lx x16 hl h x8 x hl hx x8 lh h x 256 x lh hx x 256 ll h x 1,024 x ll hx x 1,024 lh l serial programming via sd serial programming via sd hl l parallel programming via port a (3, 5) parallel programming via port a (3, 5) ll l ip mode (4, 5) ip mode (4, 5) once the master reset ( mrs1 , mrs2 ) input is high, a low on the be/ fwft input during the next low-to-high transition of clka (for fifo1) and clkc (for fifo2) will select fwft mode. this mode uses the output ready function (ora, orb) to indicate whether or not there is valid data at the data outputs (a0-a35 or b0-b17). it also uses the input ready function (ira, irc) to indicate whether or not the fifo memory has any free space for writing. in the fwft mode, the first word written to an empty fifo goes directly to the data outputs, no read request necessary. subsequent words must be accessed by performing a formal read operation. following master reset, the level applied to the be/ fwft input to choose the desired timing mode must remain static throughout fifo operation. refer to figure 4 (fifo1 master reset) and figure 5 (fifo2 master reset) for first word fall through select timing diagrams. programming the almost-empty and almost-full flags four registers in these fifos are used to hold the offset values for the almost- empty and almost-full flags. the port b almost-empty flag ( aeb ) offset register is labeled x1 and the port a almost-empty flag ( aea ) offset register is labeled x2. the port a almost-full flag ( afa ) offset register is labeled y1 and the port c almost-full flag ( afc ) offset register is labeled y2. the index of each register name corresponds to its fifo number. the offset registers can be loaded with preset values during the reset of a fifo, programmed in parallel using the fifo?s port a data inputs, or programmed in serial using the serial data (sd) input (see table 1). fs0/sd, fs1/ sen and fs2 function the same way in both idt standard and fwft modes. ? preset values to load a fifo?s almost-empty flag and almost-full flag offset registers with one of the five preset values listed in table 1, the flag select inputs must be high or low during a master reset. for example, to load the preset value of 64 into x1 and y1, fs0, fs1 and fs2 must be high when flfo1 reset ( mrs1 ) returns high. flag offset registers associated with fifo2 are loaded with one of the preset values in the same way with fifo2 master reset ( mrs2 ) toggled simultaneously with fifo1 master reset ( mrs1 ). for relevant preset value loading timing diagrams, see figure 4 and 5. ? parallel load from port a to program the x1, x2, y1, and y2 registers from port a, perform a master reset on both flfos simultaneously with fs2 high or low, fs0 and fs1 low during the low-to-high transition of mrs1 and mrs2. the state of fs2 at this point of reset will determine whether the parallel programming method has interspersed parity or non-interspersed parity. refer to table 1 for flag programming flag offset setup . it is important to note that once parallel programming has been selected during a master reset by holding both fs0 & fs1 low, these inputs must remain low during all subsequent fifo operation. they can only be toggled high when future master resets are performed and other programming methods are desired. after this reset is complete, the first four writes to fifo1 do not store data in ram but load the offset registers in the order y1, x1, y2, x2. for non- interspersed parity mode the port a data inputs used by the offset registers are (a10-a0), (a11-a0), or (a12-a0) for the IDT723656, idt723666, or idt723676, respectively. for interspersed parity mode the port a data inputs used by the offset registers are (a11-a9, a7-a0), (a12-a9, a7-a0), or (a13- a9, a7-a0) for the IDT723656, idt723666, or idt723676, respectively. the highest numbered input is used as the most significant bit of the binary number in each case. valid programming values for the registers range from 1 to 2,044 for the IDT723656; 1 to 4,092 for the idt723666; and 1 to 8,188 for the idt723676. after all the offset registers are programmed from port a, the port c full/input ready flag ( ffc /irc) is set high, and both fifos begin normal operation. refer to figure 8 for a timing diagram illustration for parallel programming of the flag offset values. interspersed parity interspersed parity is selected during a master reset of the fifo. refer to table 1 for the set-up configuration of interspersed parity. the interspersed parity function allows the user to select the location of the parity bits in the word loaded into the parallel port (a0-an) during programming of the flag offset values. table 1 ? ? ? ? ? flag programming notes: 1. x1 register holds the offset for aeb ; y1 register holds the offset for afa . 2. x2 register holds the offset for aea ; y2 register holds the offset for afc . 3. when this method of parallel programming is selected, port a will assume non-interspersed parity. 4. when ip mode is selected, only parallel programming of the offset values via port a, can be performed and port a will assume interspersed parity. 5. if parallel programming is selected during a master reset, then fs0 & fs1 must remain low during fifo operation.
13 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 csa w/ r a ena mba clka loop data a(a0-a35) i/o port function h x x x x h high-impedance none l h l x x h input none lh h l h input fifo1 write lh h h h input mail1 write l l l l x h output none ll h l h output fifo2 read l l l h x h output none ll h h h output mail2 read (set mbf2 high) lh h l l output loop the data output of fifo2 to input of fifo1 only ll h l l output loop the data output of fifo2 to input of fifo1 and put data on port a csb renb mbb clkb data b (b0-b17) outputs port function h x x x high-impedance none l l l x output none lh l output fifo1 read l l h x output none lh h output mail1 read (set mbf1 high) table 4 ? ? ? ? ? port c enable function table table 3 ? ? ? ? ? port b enable function table wenc mbc clkc data c (c0-c17) inputs port function hl input fifo2 write hh input mail2 write l l x input none l h x input none if interspersed parity is selected then during parallel programming of the flag offset values, the device will ignore data line a8. if non-interspersed parity is selected then data line a8 will become a valid bit. if interspersed parity is selected serial programming of the offset values is not permitted, only parallel program- ming can be done. ? serial load to program the x1, x2, y1, and y2 registers serially, initiate a master reset with fs2 low, fs0/sd low and fs1/ sen high during the low-to-high transition of mrs1 and mrs2 . after this reset is complete, the x and y register values are loaded bit-wise through the fs0/sd input on each low-to-high transition of clka that the fs1/ sen input is low. there are 44-, 48-, or 52- bit writes needed to complete the programming for the IDT723656, idt723666, or idt723676, respectively. the four registers are written in the order y1, x1, y2 and finally, x2. the first-bit write stores the most significant bit of the y1 register and the last-bit write stores the least significant bit of the x2 register. each register value can be programmed from 1 to 2,044 (IDT723656), 1 to 4,092 (idt723666), or 1 to 8,188 (idt723676). when the option to program the offset registers serially is chosen, the port a full/input ready ( ffa /ira) flag remains low until all register bits are written. ffa /ira is set high by the low-to-high transition of clka after the last bit is loaded to allow normal fifo1 operation. the port b full/input ready ( ffc / irc) flag also remains low throughout the serial programming process, until all register bits are written. ffc /irc is set high by the low-to-high transition of clkc after the last bit is loaded to allow normal fifo2 operation. see figure 9 timing diagram, serial programming of the almost-full flag and almost-empty flag offset values after reset (idt standard and fwft modes) . fifo write/read operation the state of the port a data (a0-a35) outputs is controlled by port a chip select ( csa ) and port a write/read select (w/ r a). the a0-a35 outputs are in the high-impedance state when either csa or w/ r a is high. the a0-a35 outputs are active when both csa and w/ r a are low. data is loaded into fifo1 from the a0-a35 inputs on a low-to-high transition of clka when csa is low, w/ r a is high, ena is high, mba is low, and ffa /ira is high. data is read from fifo2 to the a0-a35 outputs by a low-to-high transition of clka when csa is low, w/ r a is low, ena is high, mba is low, and efa /ora is high (see table 2). fifo reads and writes on port a are independent of any concurrent port b or port c operation. the state of the port b data (b0-b17) outputs is controlled by the port b chip select ( csb ). the b0-b17 outputs are in the high-impedance state when csb is high. the b0-b17 outputs are active when csb is low. table 2 ? ? ? ? ? port a enable function table
14 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range table 5 ? ? ? ? ? fifo1 flag operation (idt standard and fwft modes) table 6 ? ? ? ? ? fifo2 flag operation (idt standard and fwft modes) synchronized synchronized number of words in fifo memory (1,2) to clkb to clka IDT723656 (3) idt723666 (3) idt723676 (3) efb /orb aeb afa ffa /ira 000llhh 1 to x1 1 to x1 1 to x1 h l h h (x1+1) to [2,048-(y1+1)] (x1+1) to [4,096-(y1+1)] (x1+1) to [8,192-(y1+1)] h h h h (2,048-y1) to 2,047 (4,096-y1) to 4,095 (8,192-y1) to 8,191 h h l h 2,048 4,096 8,192 h h l l notes: 1. when a word loaded to an empty fifo is shifted to the output register, its previous fifo memory location is free. 2. data in the output register does not count as a "word in fifo memory". since in fwft mode, the first word written to an empty fifo goes unrequested to the output register (no read operation necessary), it is not included in the fifo memory count. 3. x1 is the almost-empty offset for fifo1 used by aeb . y1 is the almost-full offset for fifo1 used by afa . both x1 and y1 are selected during a fifo1 reset or port a programming. 4. the orb and ira functions are active during fwft mode; the efb and ffa functions are active in idt standard mode. notes: 1. when a word loaded to an empty fifo is shifted to the output register, its previous fifo memory location is free. 2. data in the output register does not count as a "word in fifo memory". since in fwft mode, the first word written to an empty fifo goes unrequested to the output register (no read operation necessary), it is not included in the fifo memory count. 3. x2 is the almost-empty offset for fifo2 used by aea . y2 is the almost-full offset for fifo2 used by afc . both x2 and y2 are selected during a fifo2 reset or port a programming. 4. the ora and irc functions are active during fwft mode; the efa and ffc functions are active in idt standard mode. synchronized synchronized number of words in fifo memory (1,2) to clka to clkc IDT723656 (3) idt723666 (3) idt723676 (3) efa /ora aea afc ffc /irc 000llhh 1 to x2 1 to x2 1 to x2 h l h h (x2+1) to [2,048-(y2+1)] (x2+1) to [4,096-(y2+1)] (x2+1) to [8,192-(y2+1)] h h h h (2,048-y2) to 2,047 (4,096-y2) to 4,095 (8,192-y2) to 8,191 h h l h 2,048 4,096 8,192 h h l l data is read from fifo1 to the b0-b17 outputs by a low-to-high transition of clkb when csb is low, renb is high, mbb is low and efb / orb is high (see table 3). fifo reads on port b are independent of any concurrent port a and port c operations. data is loaded into fifo2 from the c0-c17 inputs on a low-to-high transition of clkc when wenb is high, mbc is low, and ffc /irc is high (see table 4). fifo writes on port c are independent of any concurrent port a and port b operation. the setup and hold time constraints for csa and w/ r a with regard to clka as well as csb with regard to clkb are only for enabling write and read operations and are not related to high-impedance control of the data outputs. if ena is low during a clock cycle, either csa or w/ r a may change states during the setup and hold time window of the cycle. this is also true for csb when renb is low. when operating the fifo in fwft mode and the output ready flag is low, the next word written is automatically sent to the fifo?s output register by the low-to-high transition of the port clock that sets the output ready flag high. when the output ready flag is high, subsequent data is clocked to the output registers only when a read is selected using csa , w/ r a, ena and mba at port a or using csb , renb and mbb at port b. when operating the fifo in idt standard mode, the first word will cause the empty flag to change state on the second low-to-high transition of the read clock. the data word will not be automatically sent to the output register. instead, data residing in the fifo?s memory array is clocked to the output register only when a read is selected using csa , w/ r a, ena and mba at port a or using csb , renb and mbb at port b. relevant write and read timing diagrams for port a can be found in figure 10 and 15. relevant read and write timing diagrams for port b and port c, together with bus-matching and endian select operation, can be found in figure 11 to 14. loopback ( loop ) a loopback function is provided on port a and is selected by setting the loop pin low. when the loop feature is selected, the data output from fifo2 will be directed to the data input of fifo1. if loop is selected and port a is set-up for write operation via the w/ra pin being high, then data output from fifo2 will be written to fifo1, on every low-to-high transition of clka, provided csa is low and ena is high. however, fifo2 data output will not be placed on the output port a (a0-a35). if port a is set-up for read operation via the w/ra pin being low, then data output from fifo2 will be written into fifo1 on every low-to-high transition of clka, provided csa is low and ena is high. also fifo2 data will be output to port a (a0-a35). when the loop pin is high then port a operates in the normal manner. refer to table 2 for the input set-up of the loop feature. the loop operation will continue to happen provided that fifo1 is not full and fifo2 is not empty. if during a loop sequence fifo1 becomes full then any data that continues to be read out from fifo2 will only be placed on the
15 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 port a (a0-a35) lines, (provided that port a is set-up for read operation). if during a loop sequence the fifo2 becomes empty, then the last word from fifo2 will continue to be clocked into fifo1 until fifo1 becomes full or until the loop function is stopped. the loop feature can be useful when performing system debugging and remote loopbacks. see figures 34 and 35 for loopback timing diagrams. synchronized fifo flags each fifo is synchronized to its port clock through at least two flip-flop stages. this is done to improve flag signal reliability by reducing the probability of metastable events when clka operates asynchronously with respect to either clkb or clkc. efa /ora, aea , ffa /ira, and afa are synchronized to clka. efb /orb and aeb are synchronized to clkb. ffc /irc and afc are synchronized to clkc. tables 5 and 6 show the relationship of each port flag to fifo1 and fifo2. empty/output ready flags ( efa /ora, efb /orb) these are dual purpose flags. in the fwft mode, the output ready (ora, orb) function is selected. when the output ready flag is high, new data is present in the fifo output register. when the output ready flag is low, the previous data word is present in the fifo output register and attempted fifo reads are ignored. in the idt standard mode, the empty flag ( efa , efb ) function is selected. when the empty flag is high, data is available in the fifo?s ram memory for reading to the output register. when the empty flag is low, the previous data word is present in the fifo output register and attempted fifo reads are ignored. the empty/output ready flag of a fifo is synchronized to the port clock that reads data from its array. for both the fwft and idt standard modes, the fifo read pointer is incremented each time a new word is clocked to its output register. the state machine that controls an output ready flag monitors a write pointer and read pointer comparator that indicates when the fifo memory status is empty, empty+1, or empty+2. in fwft mode, from the time a word is written to a fifo, it can be shifted to the fifo output register in a minimum of three cycles of the output ready flag synchronizing clock. therefore, an output ready flag is low if a word in memory is the next data to be sent to the flfo output register and three cycles of the port clock that reads data from the fifo have not elapsed since the time the word was written. the output ready flag of the fifo remains low until the third low-to-high transition of the synchronizing clock occurs, simulta- neously forcing the output ready flag high and shifting the word to the fifo output register. in idt standard mode, from the time a word is written to a fifo, the empty flag will indicate the presence of data available for reading in a minimum of two cycles of the empty flag synchronizing clock. therefore, an empty flag is low if a word in memory is the next data to be sent to the flfo output register and two cycles of the port clock that reads data from the fifo have not elapsed since the time the word was written. the empty flag of the fifo remains low until the second low-to-high transition of the synchronizing clock occurs, forcing the empty flag high; only then can data be read. a low-to-high transition on an empty/output ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t skew1 or greater after the write. otherwise, the subsequent clock cycle can be the first synchronization cycle (see figure 16, 17, 18 and 19). full/input ready flags ( ffa /ira, ffc /irc) these are dual purpose flags. in fwft mode, the input ready (ira and irc) function is selected. in idt standard mode, the full flag ( ffa and ffc ) function is selected. for both timing modes, when the full/input ready flag is high, a memory location is free in the fifo to receive new data. no memory locations are free when the full/input ready flag is low and attempted writes to the fifo are ignored. the full/input ready flag of a flfo is synchronized to the port clock that writes data to its array. for both fwft and idt standard modes, each time a word is written to a fifo, its write pointer is incremented. the state machine that controls a full/input ready flag monitors a write pointer and read pointer comparator that indicates when the flfo memory status is full, full-1, or full-2. from the time a word is read from a fifo, its previous memory location is ready to be written to in a minimum of two cycles of the full/input ready flag synchronizing clock. therefore, an full/input ready flag is low if less than two cycles of the full/input ready flag synchronizing clock have elapsed since the next memory write location has been read. the second low-to-high transition on the full/input ready flag synchronizing clock after the read sets the full/input ready flag high. a low-to-high transition on a full/input ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t skew1 or greater after the read. otherwise, the subsequent clock cycle can be the first synchronization cycle (see figure 20, 21, 22, and 23). almost-empty flags ( aea , aeb ) the almost-empty flag of a fifo is synchronized to the port clock that reads data from its array. the state machine that controls an almost-empty flag monitors a write pointer and read pointer comparator that indicates when the fifo memory status is almost-empty, almost-empty+1, or almost-empty+2. the almost-empty state is defined by the contents of register x1 for aeb and register x2 for aea . these registers are loaded with preset values during a fifo reset, programmed from port a, or programmed serially (see the almost-empty flag and almost-full flag offset programming section). an almost-empty flag is low when its fifo contains x or less words and is high when its fifo contains (x+1) or more words. a data word present in the fifo output register has been read from memory. two low-to-high transitions of the almost-empty flag synchronizing clock are required after a fifo write for its almost-empty flag to reflect the new level of fill. therefore, the almost-full flag of a fifo containing (x+1) or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (x+1) level. an almost-empty flag is set high by the second low-to-high transition of its synchronizing clock after the fifo write that fills memory to the (x+1) level. a low-to-high transition of an almost- empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t skew2 or greater after the write that fills the fifo to (x+1) words. otherwise, the subsequent synchronizing clock cycle may be the first synchro- nization cycle. (see figure 24 and 25). almost-full flags ( afa , afc ) the almost-full flag of a fifo is synchronized to the port clock that writes data to its array. the state machine that controls an almost-full flag monitors a write pointer and read pointer comparator that indicates when the fifo memory status is almost-full, almost-full-1, or almost-full-2. the almost-full state is defined by the contents of register y1 for afa and register y2 for afc . these registers are loaded with preset values during a flfo reset, programmed from port a, or programmed serially (see almost-empty flag and almost-full flag offset programming section). an almost-full flag is low when the number of words in its fifo is greater than or equal to (2,048-y), (4,096-y), or (8,192- y) for the IDT723656, idt723666, or idt723676 respectively. an almost-full flag is high when the number of words in its fifo is less than or equal to [2,048- (y+1)], [4,096-(y+1)], or [8,192-(y+1)] for the IDT723656, idt723666, or
16 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range idt723676 respectively. note that a data word present in the fifo output register has been read from memory. two low-to-high transitions of the almost-full flag synchronizing clock are required after a fifo read for its almost-full flag to reflect the new level of fill. therefore, the almost-full flag of a fifo containing [2,048/4,096/8,192-(y+1)] or less words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [2,048/ 4,096/8,192-(y+1)]. an almost-full flag is set high by the second low-to- high transition of its synchronizing clock after the fifo read that reduces the number of words in memory to [2,048/4,096/8,192-(y+1)]. a low-to-high transition of an almost-full flag synchronizing clock begins the first synchroni- zation cycle if it occurs at time t skew2 or greater after the read that reduces the number of words in memory to [2,048/4,096/8,192-(y+1)]. otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle (see figure 26 and 27). mailbox registers each fifo has an 18-bit bypass register allowing the passage of command and control information from port a to port b or from port c to port a without putting it in queue. the mailbox select (mba, mbb and mbc) inputs choose between a mail register and a fifo for a port data transfer operation. the usable width of both the mail1 and mail2 registers matches the selected bus size for port b and c. when sending data from port a to port b via the mail1 register, the following is the case: a low-to-high transition on clka writes data to the mail1 register when a port a write is selected by csa , w/ r a, and ena with mba high. if the selected port b bus size is 18 bits, then the usable width of the mail1 register employs data lines a0-a17. (in this case, a18-a35 are don?t care inputs.) if the selected port b bus size is 9 bits, then the usable width of the mail1 register employs data lines a0-a8. (in this case, a9-a35 are don?t care inputs.) when sending data from port c to port a via the mail2 register, the following is the case: a low-to-high transition on clkc writes data to the mail2 register when a port c write is selected by wenc with mbc high. if the selected port c bus size is 18 bits, then the usable width of the mail2 register employs data lines c0-c17. if the selected port c bus size is 9 bits, then the usable width of the mail2 register employs data lines c0-c8. (in this case, c9-c17 are don?t care inputs.) writing data to a mail register sets its corresponding flag ( mbf1 or mbf2 ) low. attempted writes to a mail register are ignored while the mail flag is low. when data outputs of a port are active, the data on the bus comes from the fifo output register when the port mailbox select input is low and from the mail register when the port mailbox select input is high. the mail1 register flag ( mbf1 ) is set high by a low-to-high transition on clkb when a port b read is selected by csb , and renb with mbb high. for an 18-bit bus size, 18 bits of mailbox data are placed on b0-b17. for the 9-bit bus size, 9 bits of mailbox data are placed on b0-b8. (in this case, b9- b17 are indeterminate.) the mail2 register flag ( mbf2 ) is set high by a low-to-high transition on clka when a port a read is selected by csa , w/ r a, and ena with mba high. the data in a mail register remains intact after it is read and changes only when new data is written to the register. for an 18-bit bus size, 18 bits of mailbox data appear on a18-a35. (in this case, a0-a17 are indeterminate.) for a 9-bit bus size, 9 bits of mailbox data appear on a18-a26. (in this case, a0-a17 and a27-a35 are indeterminate.) the data in a mail register remains intact after it is read and changes only when new data is written to the register. the endian select feature has no effect on mailbox data. note that mbc must be high during master reset (until ffa /ira and ffc/ irc go high. mba and mbb are don't care inputs during master reset. for mail register and mail register flag timing diagrams, see figure 28 and 29. bus sizing port b may be configured in either an 18-bit word or a 9-bit byte format for data read from fifo1. port c may be configured in either an 18-bit word or a 9-bit byte format for data written to fifo2. the bus size can be selected independently for ports b and c. the level applied to the port b size select (sizeb) input determines the port b bus size and the level applied to the port c size select (sizec) input determines the port c bus size. these levels should be static throughout fifo operation. both bus size selections are implemented at the completion of master reset, by the time the full/input ready flag is set high, as shown in figure 2 and 3. two different methods for sequencing data transfer are available for ports b and c regardless of whether the bus size selection is byte- or word-size. they are referred to as big-endian (most significant byte first) and little-endian (least significant byte first). the level applied to the big-endian select (be) input during the low-to-high transition of mrs1 and mrs2 selects the endian method that will be active during fifo operation. this selection applies to both ports b and c. the endian method is implemented at the completion of master reset, by the time the full/input ready flag is set high, as shown in figure 2 and 3 (see endian selection section). only 36-bit long word data is written to or read from the two fifo memories on these devices. bus-matching operations are done after data is read from the fifo1 ram (port b) and before data is written to the fifo2 ram (port c) . the endian select operations are not available when transferring data via mailbox registers. furthermore, both the word- and byte-size bus selections limit the width of the data bus that can be used for mail register operations. in this case, only those byte lanes belonging to the selected word- or byte-size bus can carry mailbox data. the remaining data outputs will be indeterminate. the remaining data inputs will be don?t care inputs. for example, when a word- size bus is selected on port b, then mailbox data can be transmitted only from a0-a17 to b0-b17. when a byte-size bus is selected on port b, then mailbox data can be transmitted only from a0-a8 to b0-b8. similarly, when a word- size bus is selected on port c, then mailbox data can be transmitted only from c0-c17 to a18-a35. when a byte-size bus is selected on port c, then mailbox data can be transmitted only from c0-c8 to a18-a26. bus-matching fifo1 reads data is read from the fifo1 ram in 36-bit long word increments. since port b can have a byte or word size, only the first one or two bytes appear on the selected portion of the fifo1 output register, with the rest of the long word stored in auxiliary registers. in this case, subsequent fifo1 reads output the rest of the long word to the fifo1 output register in the order shown by figure 2. when reading data from fifo1 in byte format, the unused b9-b17 outputs are indeterminate. bus-matching fifo2 writes data is written to the fifo2 ram in 36-bit long word increments. data written to fifo2 with a byte or word bus size stores the initial bytes or words in auxiliary registers. the clkc rising edge that writes the fourth byte or the second word of long word to fifo2 also stores the entire long word in the fifo2 memory. the bytes are arranged in the manner shown in figure 3. when writing data to fifo2 in byte format, the unused c9-c17 inputs are don't care inputs.
17 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 figure 2. port b bus sizing a a d a c b b c b d c c a d d b write to fifo1 1st: read from fifo1 l l byte order on port a: be sizeb 2nd: read from fifo1 3rd: read from fifo1 4th: read from fifo1 1st: read from fifo1 1st: read from fifo1 2nd: read from fifo1 2nd: read from fifo1 h h be sizeb h l be sizeb d c 1st: read from fifo1 a b be sizeb l h 2nd: read from fifo1 3rd: read from fifo1 4th: read from fifo1 5611 drw 03 byte order on port b: a35 ? a27 a26 ? a18 a17 ? a9 a8 ? a0 b17 ? b9 b8 ? b0 b17 ? b9 b8 ? b0 b17 ? b9 b8 ? b0 b17 ? b9 b8 ? b0 b17 ? b9 b8 ? b0 b17 ? b9 b8 ? b0 b17 ? b9 b8 ? b0 b17 ? b9 b8 ? b0 b17 ? b9 b8 ? b0 b17 ? b9 b8 ? b0 b17 ? b9 b8 ? b0 b17 ? b9 b8 ? b0 (b) word size ? big endian (c) word size ? little endian (d) byte size ? big endian ( e ) byte size ? little endian
18 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range figure 3. port c bus sizing a a d a c b b c b d c c a d d b read from fifo2 1st: write to fifo2 l l byte order on port a: be sizec 2nd: write to fifo2 3rd: write to fifo2 4th: write to fifo2 1st: write to fifo2 1st: write to fifo2 2nd: write to fifo2 2nd: write to fifo2 h h be sizec h l be sizec d c 1st: write to fifo2 a b be sizec l h 2nd: write to fifo2 3rd: write to fifo2 4th: write to fifo2 5611 drw 04 byte order on port c: a35 ? a27 a26 ? a18 a17 ? a9 a8 ? a0 c17 ? c9 c8 ? c0 (b) word size ? big endian (c) word size ? little endian (d) byte size ? big endian ( e ) byte size ? little endian c17 ? c9 c8 ? c0 c17 ? c9 c8 ? c0 c17 ? c9 c8 ? c0 c17 ? c9 c8 ? c0 c17 ? c9 c8 ? c0 c17 ? c9 c8 ? c0 c17 ? c9 c8 ? c0 c17 ? c9 c8 ? c0 c8 ? c0 c17 ? c9 c8 ? c0 c17 ? c9 c8 ? c0 c17 ? c9
19 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 notes: 1. prs2 and mbc must be high during master reset until the rising edge of ffc /irc goes high. 2. if be/ fwft is high, then efa /ora will go low one clka cycle earlier than in this case where be/ fwft is low. 3. mrs2 must toggle simultaneously with mrs1 . figure 5. fifo2 master reset and loading x2 and y2 with a preset value of eight (idt standard and fwft modes) figure 4. fifo1 master reset and loading x1 and y1 with a preset value of eight (idt standard and fwft modes) notes: 1. prs1 and mbc must be high during master reset until the rising edge of ffa /ira goes high. 2. if be/ fwft is high, then efb /orb will go low one clkb cycle earlier than in this case where be/ fwft is low. clka mrs1 ffa /ira aeb afa mbf1 clkb efb /orb fs2,fs1 ,fs0 5611 drw 05 t rsts t rsth t fsh t fss t wff t wff t ref t rsf 0,1 t rsf t rsf be be/ fwft fwft t bes t beh 12 t fws (2) loop rtm low high clkc mrs2 (3) ffc /irc aea afc mbf2 clka efa /ora fs2,fs1 ,fs0 5611 drw 06 t rsts t rsth t fsh t fss t wff t wff t ref t rsf 0,1 t rsf t rsf be be/ fwft fwft t bes t beh 1 2 t fws (2) loop rtm low high
20 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range notes: 1. mrs1 must be high during partial reset. 2. if be/ fwft is high, then efb /orb will go low one clkb cycle earlier than in this case where be/ fwft is low. figure 6. fifo1 partial reset (idt standard and fwft modes) figure 7. fifo2 partial reset (idt standard and fwft modes) notes: 1. mrs2 must be high during partial reset. 2. if be/ fwft is high, then efa /ora will go low one clka cycle earlier than in this case where be/ fwft is low. clka prs1 ffa /ira aeb afa mbf1 clkb efb /orb 5611 drw 07 t rsts t rsth t wff t wff t ref t rsf t rsf t rsf 12 (2) rtm low clkc prs2 ffc /irc aea afc mbf1 clka efa /ora 5611 drw 08 t rsts t rsth t wff t wff t ref t rsf t rsf t rsf (2)
21 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 figure 9. serial programming of the almost-full flag and almost-empty flag offset values after reset (idt standard and fwft mod es) notes: 1. t skew1 is the minimum time between the rising clka edge and a rising clkc edge for ffc /irc to transition high in the next cycle. if the time between the rising edge of clka and rising edge of clkc is less than t skew1 , then ffc /irc may transition high one clkc cycle later than shown. 2. it is not necessary to program offset register bits on consecutive clock cycles. fifo write attempts are ignored until ffa /ira, ffc /irc is set high. 3. programmable offsets are written serially to the sd input in the order afa offset (y1), aeb offset (x1), afc offset (y2), and aea offset (x2). notes: 1. t skew1 is the minimum time between the rising clka edge and a rising clkc edge for ffc /irc to transition high in the next cycle. if the time between the rising edge of clka and rising edge of clkc is less than t skew1 , then ffc /irc may transition high one clkc cycle later than shown. 2. csa = low, w/ r a = high, mba = low. it is not necessary to program offset register on consecutive clock cycles. figure 8. parallel programming of the almost-full flag and almost-empty flag offset values after reset (idt standard and fwft m odes) 5611 drw 09 clka mrs1 , mrs2 ffa /ira clkc ffc /irc a0-a35 fs1,fs0 ena t fsh t wff t enh t ens2 t skew1 t ds t dh t wff 4 0,0 afa offset (y1) aeb offset (x1) afc offset (y2) aea offset (x2) first word to fifo1 1 2 (1) t fsh t fss t fss fs2 clka ffa /ira t sens t senh fs0/sd (3) t sph t sens t senh t fss t wff fs1/ sen aea offset (x2) lsb t sds t sdh t sds t sdh afa offset (y1) msb mrs1 , mrs2 4 5611 drw 10 t fss t fsh clkc 4 fs2 ffc /irc t wff t skew (1)
22 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range note: 1. written to fifo1. figure 10. port a write cycle timing for fifo1 (idt standard and fwft modes) figure 11. port c word write cycle timing for fifo2 (idt standard and fwft modes) data size table for word writes to fifo2 note: 1. be is selected at master reset; sizeb and sizec must be static throughout device operation. size mode (1) write data written data read from fifo2 no. to fifo2 sizec be c17-c9 c8-c0 a35-a27 a26-a18 a17-a9 a8-a0 lh1ababcd 2cd ll1cdabcd 2ab 5611 drw11 clka ffa /ira ena a0-a35 mba csa w/ r a t clk t clkh t clkl t enh t enh t enh t enh t dh w1 (1) w2 (1) t ens2 t ds t ens2 t ens2 t ens1 t ens1 t enh t enh t ens2 no operation high clkc wenc t enh t enh ffc /irc high 5611 drw12 c0-c17 t enh t enh mbc t dh t ds t ens2 t ens2 t ens2 t ens2
23 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 data size table for word reads from fifo1 size mode (1) data written to fifo1 read data read from fifo1 no. figure 13. port b word read cycle timing for fifo1 (idt standard and fwft modes) figure 12. port c byte write cycle timing for fifo2 (idt standard and fwft modes) note: 1. be is selected at master reset; sizeb and sizec must be static throughout device operation. size mode (1) write data written data read from fifo2 no. to fifo2 sizec be c8-c0 a35-a27 a26-a18 a17-a9 a8-a0 hh a b cd hl a b cd 1a 2b 3c 4d 1d 2c 3b 4a data size table for byte writes to fifo2 note: 1. be is selected at master reset; sizeb and sizec must be static throughout device operation. ffc /irc clkc t enh t ens2 wenc 5611 drw 13 high c0-c8 t ens2 t enh t ens2 t enh t ds t dh t enh mbc clkb renb efb /orb csb high 5611 drw 14 b0-b17 previous data t dis t a t a t ens2 t enh no operation read 1 b0-b17 t a t a read 1 read 2 read 2 read 3 t dis mbb (standard mode) (fwft mode) or t en t mdv t mdv t en sizeb be a35-a27 a26-a18 a17-a9 a8-a0 b17-b9 b8-b0 hh a b c d1a b 2 c d hl a b c d1 c d 2a b
24 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range data size table for byte reads from fifo1 size mode (1) data written to fifo1 read data read from fifo1 no. sizeb be a35-a27 a26-a18 a17-a9 a8-a0 b8-b0 hh abcd hl abcd 1a 2b 3c 4d 1d 2c 3b 4a note: 1. unused bytes b9-b17 are indeterminate for byte-size reads. note: 1. be is selected at master reset; sizeb must be static throughout device operation. figure 14. port b byte read cycle timing for fifo1 (idt standard and fwft modes) note: 1. read from fifo2. figure 15. port a read cycle timing for fifo2 (idt standard and fwft modes) efb /orb mbb csb renb clkb 5611 drw 15 high b0-b8 b0-b8 read 5 read 2 read 3 read 4 read 1 read 3 read 4 previous data read 2 no operation t dis t dis t a t a t a t a t a t a t ens2 t enh t a t a read 1 (standard mode) (fwft mode) t en t mdv t mdv t en or 5611 drw16 clka efa /ora ena mba csa w/ r a t clk t clkh t clkl t a t mdv t en t a t enh t ens2 t enh w1 (1) t enh t dis no operation a0-a35 t en t dis previous data t mdv t a or t a w2 (1) w1 (1) w2 (1) w3 (1) (fwft mode) ( standard mode) a0-a35 high t ens2 t ens2
25 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 notes: 1. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for orb to transition high and to clock the next word to the fifo1 output register in three clkb cycles. if the time between the rising clka edge and rising clkb edge is less than t skew1 , then the transition of orb high and load of the first word to the output register may occur one clkb cycle later than shown. 2. if port b size is word or byte, orb is set low by the last word or byte read from fifo1, respectively (the word-size case is shown). figure 16. orb flag timing and first data word fall through when fifo1 is empty (fwft mode) csa w r a mba a0-a35 clkb orb csb mbb ena renb b0-b17 clka 12 5611 drw17 t clkh t clkl t clk t ens2 t ens2 t enh t enh t ds t dh t skew1 t clk t clkl t ens2 t a read 1 fifo1 empty low high low low t clkh w1 high (1) t ref t ref read 2 t enh t a ira 3
26 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range notes: 1. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for efb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew1 , then the transition of efb high may occur one clkb cycle later than shown. 2. if port b size is word or byte, efb is set low by the last word or byte read from fifo1, respectively (the word-size case is shown). figure 17. efb efb efb efb efb flag timing and first data read fall through when fifo1 is empty (idt standard mode) csa w r a mba ffa a0-a35 clkb csb mbb ena renb b0-b17 clka 12 5611 drw18 t clkh t clkl t clk t ens2 t ens2 t enh t enh t ds t dh t skew1 t clk t clkl t ens2 t a read 1 fifo1 empty low high low low t clkh w1 high (1) t ref t ref read 2 t enh t a efb
27 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 notes: 1. t skew1 is the minimum time between a rising clkc edge and a rising clka edge for ora to transition high and to clock the next word to the fifo2 output register in three clka cycles. if the time between the clkc edge and the rising clka edge is less than t skew1 , then the transition of ora high and load of the first word to the output register may occur one clka cycle later than shown. 2. if port c size is word or byte, t skew1 is referenced to the rising clkc edge that writes the last word or byte write of the long word, respectively. figure 18. ora flag timing and first data word fall through when fifo2 is empty (fwft mode) mbc c0-c17 clka csa w/ r a mba wenc ena a0-a35 clkc 12 5611 drw19 t clkh t clkl t clk t ens2 t ens2 t enh t enh t ds t dh t skew1 t clk t clkl t ens2 t enh t a w1 fifo2 empty low low low t clkh high (1) t ref t dh t ds write 1 write 2 ora irc 3 old data in fifo2 output register t ref
28 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range notes: 1. t skew1 is the minimum time between a rising clkc edge and a rising clka edge for efa to transition high in the next clka cycle. if the time between the rising clkc edge and rising clka edge is less than t skew1 , then the transition of efa high may occur one clka cycle later than shown. 2. if port c size is word or byte, t skew1 is referenced to the rising clkc edge that writes the last word or byte of the long word, respectively. figure 19. efa efa efa efa efa flag timing and first data read when fifo2 is empty (idt standard mode) mbc ffc c0-c17 clka efa csa w/ r a mba wenc ena a0-a35 clkc 12 5611 drw20 t clkh t clkl t clk t ens2 t ens2 t enh t enh t ds t dh t skew1 t clk t clkl t ens2 t enh t a w1 fifo2 empty low low low t clkh high (1) t ref t ref t dh t ds write 1 write 2
29 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 notes: 1. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ira to transition high in the next clka cycle. if t he time between the rising clkb edge and rising clka edge is less than t skew1 , then ira may transition high one clka cycle later than shown. 2. if port b size is word or byte, t skew1 is referenced to the rising clkb edge that reads the last word or byte write of the long word, respectively (the word-size case is shown). figure 20. ira flag timing and first available write when fifo1 is full (fwft mode) csb mbb renb b0-b17 clkb clka csa 5611 drw21 w/ r a 12 a0-a35 mba ena t clk t clkh t clkl t ens2 t enh t a t skew1 t clk t clkh t clkl t ens2 t ens2 t ds t enh t enh t dh to fifo1 read 2 low low high low high (1) fifo1 full t wff t wff read 1 t a previous word in fifo1 output register orb ira write
30 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range notes: 1. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ffa to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew1 , then ffa may transition high one clka cycle later than shown. 2. if port b size is word or byte, t skew1 is referenced from the rising clkb edge that reads the last word or byte of the long word, respectively (the word-size case is shown). figure 21. ffa ffa ffa ffa ffa flag timing and first available write when fifo1 is full (idt standard mode) csb efb mbb renb b0-b17 clkb ffa clka csa 5611 drw22 w/ r a 12 a0-a35 mba ena t clk t clkh t clkl t ens2 t enh t a t skew1 t clk t clkh t clkl t ens2 t ens2 t ds t enh t enh t dh to fifo1 read 2 low low high low high (1) fifo1 full t wff t wff read 1 t a previous word in fifo1 output register write
31 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 notes: 1. t skew1 is the minimum time between a rising clkc edge and a rising clkc edge for irc to transition high in the next clkc cycle. if t he time between the rising clka edge and rising clkc edge is less than t skew1 , then irc may transition high one clkc cycle later than shown. 2. if port c size is word or byte, irc is set low by the last word or byte write of the long word, respectively (the word-size c ase is shown). figure 22. irc flag timing and first available write when fifo2 is full (fwft mode) csa ora mba ena a0-a35 clka irc clkc 5611 drw23 12 c0-c17 mbc wenc t clk t clkh t clkl t ens2 t enh t a t skew1 t clk t clkh t clkl t ens2 t ens2 t ds t enh t enh t dh to fifo2 previous word in fifo2 output register next word from fifo2 low w/ r a low low high (1) fifo2 full t wff t dh t ds t wff write
32 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range notes: 1. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for aeb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then aeb may transition high one clkb cycle later than shown. 2. fifo1 write ( csa = low, w/ r a = low, mba = low), fifo1 read ( csb = low, mbb = low). data in the fifo1 output register has been read from the fifo. 3. if port b size is word or byte, aeb is set low by the last word or byte read from fifo1, respectively. figure 24. timing for aeb aeb aeb aeb aeb when fifo1 is almost-empty (idt standard and fwft modes) figure 23. ffc ffc ffc ffc ffc flag timing and first available write when fifo2 is full (idt standard mode) notes: 1. t skew1 is the minimum time between a rising clka edge and a rising clkc edge for ffc to transition high in the next clkc cycle. if the time between the rising clka edge and rising clkc edge is less than t skew1 , then ffc may transition high one clkc cycle later than shown. 2. if port c size is word or byte, ffc is set low by the last word or byte write of the long word, respectively (the word-size case is shown). csa efa mba ena a0-a35 clka ffc clkc 5611 drw24 12 c0-c17 mbc enc t clk t clkh t clkl t ens2 t enh t a t skew1 t clk t clkh t clkl t ens2 t ens2 t ds t enh t enh t dh to fifo2 previous word in fifo2 output register next word from fifo2 low w/ r a low low high (1) fifo2 full t wff t wff t dh t ds write aeb clka renb 5611 drw 25 ena clkb 2 1 t ens2 t enh t skew2 t pae t pae t ens2 t enh x1 word in fifo1 (x1+1) words in fifo1 (1)
33 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 notes: 1. t skew2 is the minimum time between a rising clkc edge and a rising clka edge for afc to transition high in the next clkc cycle. if the time between the rising clkc edge and rising clka edge is less than t skew2 , then afc may transition high one clkc cycle later than shown. 2. fifo2 write (mbc = low), fifo2 read ( csa = low, w/ r a = low, mba = low). data in the fifo2 output register has been read from the fifo. 3. d = maximum fifo depth = 2,048 for the IDT723656, 4,096 for the idt723666, 8,192 for the idt723676. 4. port c size is word or byte, afc is set low by the last word or byte write of the long word, respectively. figure 27. timing for afc afc afc afc afc when fifo2 is almost-full (idt standard and fwft modes) figure 25. timing for aea aea aea aea aea when fifo2 is almost-empty (idt standard and fwft modes) figure 26. timing for afa afa afa afa afa when fifo1 is almost-full (idt standard and fwft modes) notes: 1. t skew2 is the minimum time between a rising clkc edge and a rising clka edge for aea to transition high in the next clka cycle. if the time between the rising clkc edge and rising clka edge is less than t skew2 , then aea may transition high one clka cycle later than shown. 2. fifo2 write (mbc = low), fifo2 read ( csa = low, w/ r a = low, mba = low). data in the fifo2 output register has been read from the fifo. 3. if port c size is word or byte, t skew2 is referenced to the rising clkc edge that writes the last word or byte of the long word, respectively. notes: 1. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for afa to transition high in the next clka cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then afa may transition high one clka cycle later than shown. 2. fifo1 write ( csa = low, w/ r a = high, mba = low), fifo1 read ( csb = low, mbb = low). data in the fifo1 output register has been read from the fifo. 3. d = maximum fifo depth = 2,048 for the IDT723656, 4,096 for the idt723666, 8,192 for the idt723676. 4. if port b size is word or byte, t skew2 is referenced from the rising clkb edge that reads the last word or byte of the long word, respectively. aea clkc ena 5611 drw 26 wenc clka 2 1 t ens2 t enh t skew2 t pae t pae t ens2 t enh (x2+1) words in fifo2 x2 words in fifo2 (1) afa clka renb 5611 drw 27 ena clkb 12 t skew2 t ens2 t enh t paf t ens2 t enh t paf [d-(y1+1)] words in fifo1 (d-y1) words in fifo1 (1) afc clkc ena 5611 drw 28 wenc clka 12 t skew2 t ens2 t enh t paf t ens2 t enh t paf [d-(y2+1)] words in fifo2 (d-y2) words in fifo2 (1)
34 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range figure 28. timing for mail1 register and mbf1 mbf1 mbf1 mbf1 mbf1 flag (idt standard and fwft modes) figure 29. timing for mail2 register and mbf2 mbf2 mbf2 mbf2 mbf2 flag (idt standard and fwft modes) 5611 drw29 clka ena a0-a35 mba csa w/ r a clkb mbf1 csb mbb renb b0-b17 w1 t enh t ds t dh t pmf t pmf t ens2 t enh t dis t en t mdv t pmr fifo1 output register w1 (remains valid in mail1 register after read) t enh t enh t enh t ens1 t ens1 t ens2 t ens2 5611 drw30 clkc enc c0-c17 mbc clka mbf2 csa mba ena a0-a35 w/ r a w1 t ds t dh t pmf t pmf t enh t dis t en t mdv t pmr fifo2 output register w1 (remains valid in mail2 register after read) t enh t enh t ens2 t ens2 t ens2 note: 1. if port c is configured for word size, data can be written to the mail2 register using c0-c17. in this first case, a18-a35 wi ll have valid data (a0-a17 will be indeterminate). if port c is configured for byte size, data can be written to the mail2 register using c0-c8 (c9-c17 are don't care inputs). in this second case, a18-a 26 will have valid data (a0-a17 and a27-a35 will be indeterminate). note: 1. if port b is configured for word size, data can be written to the mail1 register using a0-a17 (a18-a35 are don't care inputs) . in this first case b0-b17 will have valid data. if port b is configured for byte size, data can be written to the mail1 register using a0-a8 (a9-a35 are don't care inputs). in this se cond case, b0-b8 will have valid data (b9-b17 will be indeterminate).
35 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 clka renb clkb rt1 5611 drw31 t rsts t rsth t ref (2) b0-bn rtm efb t ref (2) w1 wx 13 4 2 1 34 2 t rtms t rtmh t a t ens2 t enh notes: 1. csb = low 2. retransmit setup is complete after efb returns high, only then can a read operation begin. 3. w1 = first word written to the fifo1 after master reset on fifo1. 4. no more than d-2 may be written to the fifo1 between reset of fifo1 (master or partial) and retransmit setup. therefore, ffa will be low throughout the retransmit setup procedure. d = 2,048, 4,096 and 8,192 for the IDT723656, idt723666 and idt723676 respectively. figure 30. retransmit timing for fifo1 (idt standard mode) notes: 1. csa = low 2. retransmit setup is complete after efa returns high, only then can a read operation begin. 3. w1 = first word written to the fifo1 after master reset on fifo2. 4. no more than d-2 may be written to the fifo1 between reset of fifo2 (master or partial) and retransmit setup. therefore, ffc will be low throughout the retransmit setup procedure. d = 2,048, 4,096 and 8,192 for the IDT723656, idt723666 and idt723676 respectively. figure 31. retransmit timing for fifo2 (idt standard mode) clkc ena clka rt2 5611 drw32 t rsts t rsth t ref (2) a0-an rtm efa w1 wx t rtms t rtmh t ref (2) 13 4 2 1 34 2 t a t ens2 t enh
36 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range clka renb clkb rt1 5611 drw33 t rsts t rsth t ref (2) b0-bn rtm orb w1 wx 13 4 2 1 34 2 t rtms t rtmh low t a t ref (2) notes: 1. csb = low 2. retransmit setup is complete after orb returns high, only then can a read operation begin. 3. w1 = first word written to the fifo1 after master reset on fifo1. 4. no more than d-2 may be written to the fifo1 between reset of fifo1 (master or partial) and retransmit setup. therefore, ira will be low throughout the retransmit setup procedure. d = 2,049, 4,097 and 8,193 for the IDT723656, idt723666 and idt723676 respectively. figure 32. retransmit timing for fifo1 (fwft mode) clkc ena clka rt2 5611 drw34 t rsts t rsth a0-an rtm ora w1 wx 13 4 2 1 34 2 t rtms t rtmh low t ref (2) t ref (2) t a notes: 1. csa = low 2. retransmit setup is complete after ora returns high, only then can a read operation begin. 3. w1 = first word written to the fifo2 after master reset on fifo2. 4. no more than d-2 may be written to the fifo2 between reset of fifo2 (master or partial) and retransmit setup. therefore, irc will be low throughout the retransmit setup procedure. d = 2,049, 4,097 and 8,193 for the IDT723656, idt723666 and idt723676 respectively. figure 33. retransmit timing for fifo2 (fwft mode)
37 commercial temperature range IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 5611 drw35 clka ena mba csa w/ r a t clk t clkh t clkl t a t mdv t en t a t ens2 t enh t enh t enh t dis no operation wn (1) wn+1 loop wn-1 (1) a0-a35 write to fifo 1 write to fifo 1 t ens2 t ens2 notes: 1. data is read from fifo2 and written into fifo1 & placed on port a simultaneously. the first data word written into fifo1 is t he previous data word (wn-1) 2. all fifo status flags operate as normal, based on the contents of respective fifo's. 3. loopback is available in both standard idt and fwft modes. the diagram above is for both. figure 34. loopback operation (fifo2 data transfer to fifo1 and port a) 5611 drw36 clka ena mba csa w/ r a t clk t clkh t clkl t ens2 t a t mdv t en t a t enh t enh t enh t dis no operation wn (1) wn+1 a0-a35 loop (4) write to fifo 1 high-z wn-1 (1) write to fifo 1 write to fifo 1 t ens2 t ens2 notes: 1. data is read from fifo2 and written into fifo1 only. the data from fifo2 is not placed on port a. port a is held in the high impedance state. 2. all fifo status flags operate as normal, based on the contents of respective fifo's. 3. loopback is available in both standard idt and fwft modes. the diagram above is for both. 4. write operations to fifo1 cannot be accessed via port a. figure 35. loopback operation (fifo2 data transfer to fifo1)
38 IDT723656/723666/723676 cmos triple bus syncfifo tm with bus matching 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 commercial temperature range note: 1. includes probe and jig capacitance. figure 36. load circuit and voltage waveforms 4665 drw 37 parameter measurement information from output under test 30 pf 1.1k ? 5.0v 680 ? propagation delay load circuit 3v gnd timing input data, enable input gnd 3v 1.5v 1.5v voltage waveforms setup and hold times voltage waveforms pulse durations voltage waveforms enable and disable times voltage waveforms propagation delay times 3v gnd gnd 3v 1.5v 1.5v 1.5v 1.5v t w output enable low-level output high-level output 3v ol gnd 3v 1.5v 1.5v 1.5v 1.5v oh ov gnd oh ol 1.5v 1.5v 1.5v 1.5v input in-phase output high-level input low-level input v v v v 1.5v 3v t s t h t plz t phz t pzl t pzh t pd t pd (1)
39 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-360-1753 san jose, ca 95138 fax: 408-284-2775 email: fifohelp@idt.com www.idt.com ordering information blank g pf 12 15 l 723656 723666 723676 5611 drw38 commercial (0 o c to +70 o c) green thin quad flat pack (tqfp, pk128-1) low power 2,048 x 36 x 2 ? triple bus syncfifo ? with bus-matching 4,096 x 36 x 2 ? triple bus syncfifo ? with bus-matching 8,192 x 36 x 2 ? triple bus syncfifo ? with bus-matching xxxxxx device type xxx x power speed package x clock cycle time (t clk ) speed in nanoseconds commercial only process/ temperature range x notes: 1. industrial temperature range is available by special order. 2. green parts available. for specific speeds and packages contact your sales office. datasheet document history 12/21/2000 pgs. 13 and 22. 03/21/2001 pgs. 7 and 8. 08/01/2001 pgs. 7, 9, 10 and 39. 11/03/2003 pg. 1. 02/04/2009 pgs. 1, and 39.

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